1. Field of the Invention
The present invention is directed toward the field of electronic circuits, and more particularly toward a high-speed finite impulse response (“FIR”) equalizer.
2. Art Background
Data communication systems transport data at speeds defined by a predetermined data rate. The speed of transmitting data in modem broadband communication systems has rapidly increased in recent years. Today, data rates as high as 40 gigabits per second (“Gbps”) are required, as exemplified by the OC-768 optical networking standard.
Some data communication systems utilize serial data transmission. For example, electronic circuits utilize serial data transmission to transmit data among one or more circuits. In general, serial data transmission involves transmitting bits in a single bit stream at a predetermined data rate. The data rate is expressed as the number of bits transmitted per second (“bps”). Typically, to transfer data between circuits, the sending circuit employs a transmitter that modulates and sends data using a local clock. The local clock provides the timing for the bit rate. The receiving circuit employs a receiver to recover the data, and in some cases, the clock. The receiver circuit recovers the serial bit stream of data by sampling the bit stream at the specified data rate.
Equalizer circuits are used to condition and shape the frequency content of signals for subsequent processing. High-speed serial links, such as copper and fiber links, benefit from equalization of both received and/or transmitted signals. One type of equalizer is known as a finite impulse response (“FIR”) filter. In general, a FIR filter shapes the waveform to exhibit particular characteristics. A FIR filter typically consists of delay elements, multipliers, and a summing circuit. The multipliers include coefficients that correspond to the impulse response of the filter, and the summing circuit sums the constituent components output from the multipliers. Typically, FIR filters are implemented in digital logic. For a digital implementation, shift registers are used as the delay elements (i.e., a signal sample of the signal is shifted through a series of registers to delay the signal). However, for high-speed circuit applications, such as high-speed serial links, the digital solutions are not feasible. Consequently, FIR filters employed in high-speed applications operate on either discrete time or continuous time analog signals.
As disclosed herein, the present invention includes techniques for FIR filter equalization for use in high-speed applications.